Implementation of Algorithms For Multi-Channel Digital Monitoring Receiver

Monitoring Receivers form an important constituent of the Electronic support. In Monitoring Receiver we can monitor, demodulate or scan the multiple channels. In this project, the Implementation of algorithm for multi channel digital monitoring receiver. The implementation will carry out the channelization by the way of Digital down Converters (DDCs) and Digital Base band Demodulation. The Intermediate Frequency (IF) at 10.7 MHz will be digitalized using Analog to Digital Converter (ADC) with sampling frequency 52.5 MHz and further converted to Base band using DDCs. Virtually all the digital receivers perform channel access using a DDC. The Base band data will be streamed to the appropriate demodulators. Matlab Simulink will be used to simulate the logic modules before the implementation. This system will be prototyped on an FPGA based COTS (Commercial-off-the-shelf) development board. Xilinx System Generator will be used for the implementation of the algorithms.